Simplicity 7018H manuály

Simplicity 7018H Specifikace (477 strany)

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TMS320LF/LC240x

1

DSP Controllers

1

Reference Guide

1

Read This First

3

Notational Conventions

4

Trademarks

7

Contents

10

Interface (SCI) module

11

RAM, layout, and operations

13

Examples

24

Introduction

25

1.1 TMS320 Family Overview

26

1.3 Peripheral Overview

29

1.4 ’240x Highlights

30

’240x Highlights

31

Chapter 2

32

2.1 Architecture Summary

33

2.2 Configuration Registers

34

Configuration Registers

35

Table 2–2

39

Figure 2–5

44

2.4.1 Interrupt Hierarchy

45

2.4.3 Interrupt Acknowledge

46

2.5 Interrupt Vectors

47

Interrupt Vectors

48

2.5.2 Software Hierarchy

49

2.5.3 Nonmaskable Interrupts

49

must not

50

Interrupt Operation Sequence

51

2.7 Interrupt Latency

52

2.8 Sample ISR Code

53

2.9 CPU Interrupt Registers

54

CPU Interrupt Registers

55

Figure 2–10

58

Bits 14–0 IRQ1.14–IRQ1.0

60

Bits 15–0 IRQ2.15–IRQ2.0

61

2.11 Reset

66

2.12 Illegal Address Detect

66

15 14–3 2 1 0

67

XINT1 flag

67

RC-0 R-0 RW-0 RW-0 RW-0

67

XINT2 flag

68

Chapter 3

69

3.2 Flash

70

3.4 Program Memory

78

Program Memory

79

3.5 Data Memory

80

Data Memory

81

Figure 3–9. Data Memory Pages

82

Data Page 0 Address Map

82

Data Memory Configuration

83

3.6 I/O Space

84

Visibility

85

3.8 Program and Data Spaces

88

3.9 I/O Space

88

3.10 Wait-State Generation

89

Wait-State Generation

90

Chapter 4

92

4.1 Pins

93

4.2 Phase-Locked Loop

93

4.3 Watchdog Timer Clock

93

4.4 Low-Power Modes

94

4.4.2.1 Reset

95

4.4.2.2 External interrupts

95

4.4.2.3 Wake Up Interrupts

95

4.4.2.4 Peripheral interrupts

96

5.3 I/O MUX Control Registers

101

I/O Mux Control Register A

101

I/O MUX Control Registers

102

Digital Input/Output (I/O)

103

Event Manager (EV)

112

Software change:

116

6.1.2 EV Pins

117

6.1.4 EV Registers

120

6.1.5 EV Interrupts

120

CPU response

121

PIE response

121

Interrupt software

121

Timer Functional Blocks

125

GP Timer Inputs

126

GP Timer Outputs

127

GP Timer Compare Registers

128

GP Timer Period Register

128

GP Timer Compare Output

129

Timer Counting Direction

129

Timer Clock

129

QEP-Based Clock Input

130

GP Timer Synchronization

130

GP Timer in Emulation Suspend

131

GP Timer Interrupts

131

Stop/Hold Mode

132

Continuous Up-Counting Mode

132

General-Purpose (GP) Timers

133

TxPR = 3

135

PWM Transition

137

Symmetric Waveform Generation

138

Output Logic

140

PWM Operation

147

6.4 Compare Units

148

Compare Inputs/Outputs

149

Compare Operation Modes

149

Operation

149

6.4.1 Compare Units Registers

150

Compare Units

151

6.4.2 Compare Unit Interrupts

156

6.4.3 Compare Unit Reset

156

Dead Band Generation

161

6.5.3 Output Logic

164

PWM Signal Generation

166

Dead Band

166

Figure 6–22

168

Circuits (x = 1, 3, or 5)

169

6.7 Space Vector PWM

171

Space Vector PWM

172

The Field Orientation Princi

173

Software

174

Space Vector PWM Hardware

174

Space Vector PWM Waveforms

175

The Unused Compare Register

175

6.8 Capture Units

177

Capture Units

178

6.8.1 Capture Unit Features

179

Capture Unit Setup

181

First Capture

187

Second Capture

187

Third Capture

187

6.8.5 Capture Interrupt

188

6.9.1 QEP Pins

189

6.9.2 QEP Circuit Time Base

189

QEP Circuit

190

6.9.4 QEP Counting

191

Event Manager (EV) Interrupts

193

Interrupt Generation

195

Interrupt Vector

196

Chapter 7

209

7.1 Features

210

Features

211

7.2 ADC Overview

212

ADC Overview

213

7.2.2 Basic Operation

215

7.3 ADC Clock Prescaler

224

ADC Clock Prescaler

225

7.4 Calibration

226

7.5 Self-Test

227

7.6 Register Bit Descriptions

228

Register Bit Descriptions

229

7.6.2 ADC Control Register 2

231

Bits 15–12 Reserved

237

ADC Conversion Clock Cycles

242

CPS = 0 and ACQ = 0:

243

CPS = 1 and ACQ = 1:

243

Chapter 8

244

8.1 Differences vs. ’C240 SCI

245

Differences vs. ’C240 SCI

246

Figure 8–1. SCI Block Diagram

247

8.1.2 Architecture

248

8.1.3 SCI Module Registers

249

SCI Programmable Data Format

251

address

252

is being addressed

254

SCI Block

254

don’t care

255

MSB Parity

256

LSB Stop

256

8.4 SCI Communication Format

257

Three bits per character

258

SCI Communication Format

259

8.5 SCI Port Interrupts

260

Baud-Select Registers

261

8.6 SCI Module Registers

262

SCI Module Registers

263

8.6.2 SCI Control Register 1

265

8.6.3 Baud-Select Registers

268

8.6.4 SCI Control Register 2

269

8.6.6.1 Emulation Data Buffer

272

8.6.6.2 Receiver Data Buffer

273

Chapter 9

275

9.1 Differences vs. ’C240 SPI

276

State control logic

277

9.2 SPI Control Registers

278

SPI Control Registers

279

9.3 SPI Operation

280

Master Mode

281

Slave Mode

282

9.4 SPI Interrupts

283

9.4.6 Data Format

284

Baud Rate Determination

285

9.4.8 SPI Clocking Schemes

286

SPI Interrupts

287

CLOCK POLARITY = 1

288

9.4.11 Data Transfer Example

289

9.5 SPI Control Registers

291

SPI Clocking

292

9.6 SPI Example Waveforms

303

SPI Example Waveforms

304

16 bits of transmission.)

307

CAN Controller Module

309

10.1 Introduction

310

10.2.1 CAN Protocol Overview

311

Figure 10–1. CAN Data Frame

312

Control/Status Registers

313

Mailbox RAM

313

10.2.3 Memory Map

314

Overview of the CAN Network

315

Table 10–3. Mailbox Addresses

316

10.3 Message Objects

317

10.3.1 Mailbox Layout

318

Message Objects

319

10.3.2 Message Buffers

320

10.3.4 Transmit Mailbox

321

10.3.5 Receive Mailbox

321

Receiving a Remote Request

322

Sending a Remote Request

323

Local Acceptance Mask (LAM)

324

10.4 CAN Control Registers

326

CAN Control Registers

327

Soft mode

331

Free mode

331

CAN Bit Timing

335

Figure 10–17. CAN Bit Timing

335

= 20 MHz

335

10.5 Status Registers

336

Status Registers

337

Auto Bus-On

338

10.6 Interrupt Logic

340

Interrupt Logic

341

10.7 Configuration Mode

344

10.8 Power-Down Mode (PDM)

345

10.9 Suspend Mode

346

Table 10–5. CAN Notation

347

Suspend Mode

348

Watchdog (WD) Timer

349

11.1 Watchdog Timer Features

350

Watchdog Timer Features

351

11.2 Control Registers

352

11.2.2 Operation of WD Timers

353

11.2.3 WD Prescale Select

353

11.2.4 Servicing the WD Timer

353

11.2.4.1 WD Reset

354

11.2.4.2 WD Check Bit Logic

355

11.2.4.3 WD Setup

355

11.3.1 WD Counter Register

356

11.3.2 WD Reset Key Register

357

Watchdog Control Registers

358

Chapter 12

359

12.1 General

360

12.2 Event Manager

361

12.6 Watchdog Timer

362

Chapter 13

363

13.1 Introduction

364

3.3-V DSP for

365

Digital Motor Control

365

13.2 ’24x–’240x DSP Overview

366

13.3 Memory Map

367

13.3.2 Data Space

368

13.3.3 I/O Space

369

13.4 Flash Program Memory

370

Flash Program Memory

371

Bits 15–4 Reserved

377

13.5 System Features

378

13.5.2 Watchdog Clock

379

System Features

380

13.6 Digital I/O (GPIO Pins)

382

Digital I/O (GPIO Pins)

383

Event Manager Module (EVB)

385

Appendix A

386

Table A–1

387

Program Examples

394

240x.cmd

395

Table B–2. Program Examples

396

B.2 Program Examples

397

TMS320F240x Boot ROM Loader:

435

Protocols and Interfacing

435

C.1 Introduction

436

C.2 Protocol Definitions

440

C.2.2.1 Baud Rate Protocol

441

C.2.2.2 Data Transfer

442

Protocol Definitions

443

Glossary

454

External flag pin

468

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